1. Field of the Invention
The present invention relates to an amplifying circuit, and particularly to a class AB push-pull amplifying circuit.
2. Description of the Related Art
FIG. 6 is a schematic view showing a circuit configuration for an operational amplifier 2, which is a conventional class AB push-pull amplifying circuit. The operational amplifier 2 operates according to a voltage potential difference VIN, in which voltage signals V+ and V− are input at a non-inverting input terminal NIN+ and an inverting input terminal NIN−, respectively (VIN≡V+−V−). The operational amplifier 2 outputs an output voltage signal VOUT, in which VIN is amplified, from an output terminal NOUT.
The operational amplifier 2 has pre-stage amplifiers 10, 12, and an output stage circuit 14. The output stage circuit 14 is a push-pull circuit composed of transistors Tr1, Tr2. Tr1 connects a drain-source channel between a positive electrical supply VCC and NOUT, and Tr2 connects a drain-source channel between NOUT and a ground potential GND.
Tr1 is controlled by an output of the pre-stage amplifier 10, and Tr2 is controlled by an output of the pre-stage amplifier 12. In response to the fact that Tr1 and Tr2 are both n-channel MOS transistors, the differential input VIN to the operational amplifier 2 is fed to the pre-stage amplifier 10 and the pre-stage amplifier 12 with mutually opposite polarities. Each of the pre-stage amplifiers 10, 12 operates as a class AB amplifier, whereby the output stage circuit 14 operates as a class AB push-pull amplifying circuit.
FIG. 7 is a signal waveform diagram that illustrates an operation of the operational amplifier shown in FIG. 6. The vertical axis of each signal waveform (a) to (c) represents the signal value, and the horizontal axis represents time. The signal waveform (a) shown in FIG. 7 depicts a single-period sine wave as an example of the differential input VIN of the operational amplifier. The signal waveforms (b), (c) shown in FIG. 7 depict the change over time of drain currents ID1, ID2 in Tr1, Tr2, respectively, with the current flowing to the output terminal NOUT in the positive direction. A signal waveform (d) shown in FIG. 7 depicts the change over time in an output current IOUT that is formed on the output terminal NOUT.
As described above, the pre-stage amplifiers 10, 12 operate as class AB amplifiers, and the operating points on the amplifiers are biased in the positive direction in an amount equal to a prescribed voltage vBIAS. The bias voltage vBIAS may be, e.g., approximately 0.7 V, which is the potential difference of a p-n junction. The pre-stage amplifiers 10, 12 output the bias voltage vBIAS when the respective differential inputs are zero or negative; and, when the differential inputs are positive, a voltage variance in response to the differential inputs fed to each pre-stage amplifier 10, 12 occurs on the output terminal based on vBIAS. Since the differential input fed to the pre-stage amplifier 10 is VIN, the output voltage changes to exceed vBIAS in the positive period P+ of VIN. The output of the pre-stage amplifier 10 is applied to the gate of Tr1, and the change in ID1 illustrated by the signal waveform (b) of FIG. 7 occurs. Specifically, Tr1 increases the current ID1 that flows to NOUT in the positive period P+ of VIN; and, during other periods, an idle current iBIAS corresponding to vBIAS is caused to flow. By contrast, the differential input of the pre-stage amplifier 12 is −VIN; therefore, the output voltage changes to exceed vBIAS in the negative period P− of VIN. The output of the pre-stage amplifier 12 is applied to the gate of Tr2, and the change in ID2 illustrated by the signal waveform (c) of FIG. 7 occurs. Specifically, Tr2 increases the current ID2 that is drawn from NOUT in the negative period P− of VIN; and, during other periods, an idle current iBIAS corresponding to vBIAS is drawn from NOUT.
The current IOUT combined ID1 and ID2 is formed on NOUT, and VOUT is formed according to the load connected to NOUT. An output signal waveform that varies according to VIN is obtained on NOUT as a result of the combining.
An idle current substantially does not appear in the output current IOUT because the iBIAS associated with Tr1 and Tr2 respectively cancel each other out in the output terminal NOUT. Specifically, a problem is presented in that the idle current iBIAS passes from the power supply VCC to GND via Tr1, Tr2, and electricity is wastefully consumed. In particular, a large transistor is used in the output stage circuit 14 in order to ensure load driving capability. The iBIAS accordingly becomes larger, and more electricity is wastefully consumed.
[Patent document no. 1] Japanese Laid-open Patent Application No. 2003-115729.